The present disclosure relates to a semiconductor device having a stacking structure of two chips, a solid-state imaging device, and a camera system.
Traditionally, for an imaging device, two chips, a CMOS image sensor (CIS) chip and an image processing chip, are each mounted in a package and assembly is carried out as a module.
Alternatively, each chip is COB (Chip On Board) mounted in some cases.
In recent years, in the case of mounting an imaging device in a cellular phone or the like, reduction in the mounting area and miniaturization are required, and an SOC (System-On-Chip) to integrate the above-described two chips into one chip has been developed.
However, in the process in which the CIS process and the high-speed logic process are mixed for the integration into one chip, not only that the number of steps is increased and the cost is high but also that it is difficult to keep both of the analog characteristics and the logic characteristics favorable, which possibly leads to characteristic deterioration of the imaging device.
So, a method of assembling the above-described two chips at the chip level to achieve both of miniaturization and characteristic enhancement has been proposed (refer to Japanese Patent Laid-open Nos. 2004-146816 and 2008-85755).